Structure and manufacturing method of UMOSFET

Technical field

The invention relates to the semiconductor technical field, in particular to a high-voltage UMOSFET structure.

Background technique

Wide band-gap semiconductor silicon carbide (SiC) has become a key material in the study of high-power devices because of its large band-gap width, high thermal conductivity, high critical breakdown electric field, high electron saturation speed and strong anti-radiation ability. At the same time, because the silicon carbide material has a strong compatibility with the silicon integrated circuit process, the difficulty of production and manufacturing is greatly reduced. At present, the research and production of silicon carbide power devices abroad has been carried out, and the application advantages of silicon carbide power devices in ships, satellites, weapons, communications, automobiles, military and civilian applications are incomparable to some traditional material power devices.

4H-SiC can become a candidate semiconductor material for applications in special environments such as high frequency, high temperature, radiation resistance and high voltage and high power, which has its unique advantages, mainly in the following points:

(1) Large band gap width: Large band gap width is the main reason why SiC semiconductor materials can become the preferred material in high temperature resistance and radiation resistance environment. The large band gap makes the intrinsic carrier concentration of the material very low, and also reduces the intrinsic excitation of the carriers inside the semiconductor. In theory, SiC semiconductor materials can work normally at 1000 ° C. Even in the special environment such as high temperature and high radiation, the device will not have too many intrinsic carriers, which can reduce the influence of intrinsic carriers on the device characteristics, so that the device can work more stably.

(2) High electron saturation speed: in the high-frequency application environment, the characteristic frequency of the device is inversely proportional to the electron transit time, and the electron saturation speed is directly related to the frequency characteristics of the high-frequency device. It can be seen from the above table that the electron saturation drift speed of SiC is 2.0×107cm/s, which is twice that of Si materials. Such high electron saturation speed makes SiC based devices widely used in high-speed electronic devices and high-frequency device environments.

(3) High critical breakdown electric field: The critical breakdown electric field is a very important parameter that affects the voltage resistance of power semiconductor devices. The critical breakdown electric field of SiC semiconductor materials is relatively large, about 3MV/cm, which is 8-10 times that of GaAs and Si materials. Under the same voltage conditions, compared with the characteristic on-resistance of the Si-based device, the characteristic on-resistance of the sic-based device is only 1\200 ~ 1\100 of the characteristic on-resistance of the Si-based device, and the on-loss of the device will be significantly reduced. Similarly, under the same characteristic on-resistance, the breakdown voltage of SIC-based devices is 10 to 20 times that of Si-based devices.

(4) High thermal conductivity: High thermal conductivity makes SiC based power devices can be widely used in high temperature, high-power environment another very important factor. High thermal conductivity means that it has a high heat dissipation efficiency, which is conducive to the rapid dissipation of the heat generated by the power device in the working state, so that the device will not fail because of high temperature.

The Chinese patent CN111799333A discloses a UMOSFET structure with an electric field modulation region, including an N+ substrate, an N-drift region, a current spreading layer, and a P-body region arranged successively from bottom to top. The P-body region is provided with an N+ source region and a P+ source region. It also includes a groove, which runs through the N+ source region, the P-body region and the current expansion layer, and the bottom of the groove is located in the N-drift region; A P+ shielding layer is arranged under the trench, the inner wall of the trench is provided with a grid oxide film, and the grid oxide film is provided with a grid; An electric field modulation region is arranged below the P-body region, and the electric field modulation region runs through the current spreading layer, and the bottom of the electric field modulation region is located in the N-drift region; There is a gap between the field modulation area and the groove; The electric field modulation region includes an N-type region embedded with a P-type region. The disadvantage of the patent is that it does not solve the problem of excessive grid oxygen electric field, and does not ensure the long-term reliability of the device to a maximum extent.

Content of invention

The main purpose of the invention is to provide a UMOSFET structure using high voltage 4H-SiC semiconductor material to solve the problem of device failure and excessive on-resistance caused by high gate oxygen electric field existing in the present technology, and at the same time, it can also improve the breakdown voltage of the device, improve the stability of the device, and achieve the purpose of optimizing the performance of the device. So that it can be better used in high-power semiconductor devices.

To realize the above purpose, the invention provides the following scheme: the invention provides a UMOSFET structure using a high voltage 4H-SiC semiconductor material, which is characterized in that it comprises a drain arranged successively from bottom to bottom, an N+ substrate, a first n-drift region, a p/n alternating buffer layer, a second n-drift region, and a trench; The inner wall of the trench is provided with a grid oxide film, the grid oxide film is provided with a grid, both sides of the grid are provided with N+ source region, P-body region, P+ source region, the N+ source region, P+ source region is provided with a source on the surface of the N+ source region, P+ source region, the groove through the N+ source region, P-body region, the bottom of the groove is located in the second n-drift region; A stepped gate pn junction composed of P-type polysilicon and N-type polysilicon coated by a gate oxide film is arranged below the gate; The p/n alternating buffer layer is arranged with P-type polysilicon and N-type polysilicon successively arranged alternately; The N-type doping coating is arranged between the groove and the p/n alternating buffer layer, and the p+ gate oxygen protection zone is arranged inside the N-type doping coating, and the P+ gate oxygen protection zone contacts the gate oxide film at the bottom of the groove.

Preferably, the penetration depth of the p+ gate oxygen protection does not exceed the bottom depth of the N-type doping encapsulation.

Preferably, the grid groove depth is greater than 2μm.

Preferably, the p region doping concentration in the p/n buffer layer is 3×10

Preferably, the p/n buffer layer thickness is greater than 0.8μm.

Preferably, the distance between the p/n buffer layer and the tank bottom is 1.0-1.5μm.

A method for manufacturing a UMOSFET using a high voltage 4H-SiC semiconductor material comprises the following steps:

Step 1: First, a layer of N-type 4H-SiC lower drift layer is grown on the N-type 4H-SiC substrate, and then a layer of N-type 4H-SiC buffer layer is grown on the N-type 4H-SiC lower drift layer.

Step 2: A lithographic mask plate is placed in the lower drift layer of N-type 4H-SiC, and the mask plate is etched and perforated to form a P-type 4H-SiC buffer by ion implantation, forming a p/ N-type alternating buffer layer;

Step 3: The mask plate formed on the N-type 4H-SiC lower drift layer is removed, the N-type 4H-SiC upper drift layer is epitaxically grown on the p/ N-type alternating buffer layer, and a layer of N-type SiC is grown on the 4H-SiC substrate. The concentration of the grown N-type SiC is higher than the concentration of the device drift region. The mask treatment is performed on both sides of the N-type SiC, and N-type doping region is formed by ion implantation. Adjacent to p/n type alternate buffer layer;

Step 4: Remove the mask plate, continue to epitaxy N-type SiC, the concentration is consistent with the drift region, and then continue to grow P-type SiC, the concentration is the P-type base region;

Step 5: Perform ion implantation to form the p+ region at the edge of the P-type base region, and then perform ion implantation on the structure formed in step 4 to form the n+ region connecting the source region and channel;

Step 6: For etching treatment, first dig a narrow slot in the middle line of the device with a deeper depth, and then dig a wide slot in the middle line with a shallower depth to form the first and second stairs;

Step 7: Ion implantation is performed at the formed groove to form a p+ gate oxygen protection zone, forming a depth not exceeding the bottom of the N-type region to form the bottom diffusion area of the nw region;

Step 8: A layer of N-type polysilicon is deposited in the grid, and then a layer of P-type polysilicon is deposited, and gate oxygen is grown on the surface of the grid to form pn junction in the grid;

Step 9: Fill polysilicon and make gate; At the same time, metal is used to make the source and drain electrode, and finally form a UMOSFET using a high-voltage 4H-SiC semiconductor material.

The invention has the following technical effects:

1. By setting p+ grid oxygen protection area, the current path is effectively realized to solve the problem of too high grid oxygen electric field.

2. Through the presence of the ladder gate pn junction, the space charge region formed by the p+ gate oxygen protection region moves towards the device center line by taking advantage of the fact that the second step (that is, the shorter step at the bottom of the gate) is shorter than the first step (that is, the longer step at the top of the gate), so that the electrons enter the drift region after flowing through the p base region, so that the electrons are less blocked when diffusing downward in the drift region. Thus, the on-resistance is greatly reduced, and the problem of the sharp increase of on-resistance caused by the existence of p+ gate oxygen protection zone is solved.

3, by using p/n alternating buffer layer instead of p+-SiC shielding zone, reduce the JFET resistance formed by p+-SiC shielding zone and P-body zone, so that in the off state, the space charge zone generated between each p zone to protect the gate oxide layer, reduce the gate oxygen electric field, and increase the breakdown voltage; In the open state, n region is used to provide a flow path for the current, so that the electrons in the source region can flow smoothly through the channel to the drain, which can effectively reduce the on-resistance.