Double recessed stepped buffer gate 4H-SiC metal semiconductor field effect tube

Background technology:

Silicon carbide (sic) has received a lot of attention due to its excellent electrical properties (e.g., band gap width, high saturated electron mobility, and high thermal conductivity). It has been widely used in extremely high temperature, high power and high radiation environments. 4H-sicmesFETs based on 4h-sic (4H-sicMESFETs) occupy a very important position in high power applications and have become a research hotspot in recent years. However, in the prior art, only a small increase in drain current density or breakdown voltage is achieved, and even the performance of the other must be sacrificed to improve one of the two, because there is a mutual constraint between current density and breakdown voltage, which limits the effective improvement of power density. The prior art discloses a stepped buffer gate structure 4h-sicmesfet(sbg4h-sicmesfet), which has outstanding breakdown characteristics but slightly reduced current density. Therefore, researchers still need to find potential ways to maximize the breakdown voltage and saturation drain current density (preferably both at the same time) to meet the increasing demand for power density.



Technical implementation elements:

Aiming at the above defects in the prior art, the invention provides a double-groove stepped buffer gate 4h-sic metal semiconductor field effect tube and a modeling and simulation method, which can improve the breakdown voltage and saturation drain current density at the same time.

The double-groove stepped buffer gate 4h-sic metal semiconductor field effect tube comprises a 4h-sic semi-insulating substrate layer, a P-type buffer layer, a first groove and a second groove, and an N-type channel layer;

The upper end face of the N-type channel layer is respectively the source cap layer and the drain cap layer. The upper end face of the source cap layer is provided with a source electrode, and the upper end face of the drain cap layer is provided with a drain electrode. A grid is formed between the source cap layer and the drain cap layer. A stepped buffer grid layer is arranged between the gate and the upper surface of the N-type channel layer. A field plate is formed by extending a certain distance from the drain to the gate, and a passivation layer si3n4 is arranged between the drain and the gate.

The first groove setup and the second groove are arranged on top of the P-type buffer layer, where the first groove is located below the gate and the second groove is located below the drain cap layer and the field plate.

Preferably, the first and second grooves are of the same depth and length, 0.15μm and 1μm, respectively.

Preferably, a small table post is arranged between the first groove and the second groove, and the length of the small table post is 0.2μm.

Preferably, the thickness and length of the source and drain are the same, 0.2μm and 0.5μm respectively; The thickness and length of the grid are 0.2μm and 0.7μm, respectively. The gate source spacing, gate drain spacing, gate and field plate spacing are 0.5μm, 0.7μm and 0.3μm, respectively.

Preferably, the thickness of the N-type channel layer and P-type buffer layer are 0.25μm and 0.5μm, respectively, and the doping concentration is 3×1017cm-3 and 1.4×1015cm-3, respectively.